In a cellular phone etc., communication is performed by using high frequency signals in the 800 MHz to 2.3 GHz bandwidth. This frequency is relatively high; therefore, in selecting a device using a power amplifier (PA) for amplifying a transmission power, a low noise amplifier (LNA) for amplifying a reception signal, a switch (SW) for switching signals etc., often the high frequency characteristic is very important and a compound semiconductor such as GaAs is used in place of the usually used Si semiconductor.
A high frequency integrated circuit using a GaAs or other compound semiconductor generally has excellent high frequency characteristics, but often is very weak against the ESD (electrostatic discharge). One of the reasons for this is that each device used is vulnerable to ESD or other noise due to the improvement of the high frequency characteristics. Further, when introducing a protection device, since the handled frequency is high, the adverse influence due to the parasitic capacitance cannot be avoided. Sufficient countermeasures are often not taken.
FIG. 4A shows an example of the circuit configuration of an ESD protection circuit 40 equipped with a conventional ESD protection device. Between an I/O (input/output) terminal 42 and a GND (ground), a diode 43 is connected for countering ESD. In the case of a positive DC (direct current) bias or an RF signal having an RF amplitude of a forward threshold voltage (VI) or less of the diode 43, this diode 43 appears to have a relatively high impedance and does not exert any influence upon the circuit characteristics. On the other hand, when noise having a voltage amplitude like ESD is applied to the I/O (input/output) terminal 42, it exceeds a breakdown voltage (Vb) in a reverse direction of the protection diode 43, the noise is pulled into the GND, and damage to the internal portion of the circuit (high frequency circuit 41) can be avoided.
FIG. 4B shows a voltage-current characteristic of the diode. The abscissa indicates a voltage applied to the diode 43, and the ordinate indicates a value of current flowing in this diode 43. As apparent from this graph, when voltage is applied in the forward direction, the current flows from Vf (forward directional threshold voltage), while when the voltage is applied in the reverse direction, almost no current flows up to Vb (breakdown voltage). However, when the application voltage in the reverse direction exceeds Vb, the current begins to abruptly flow. As a result, a resistance of the diode 43 (ΔV/ΔI) becomes small.
When forming a protection diode on an Si substrate, a positive pole or negative pole of the diode can be obtained at a substrate bulk side having a low resistance. On the other hand, when forming the diode 43 as in FIG. 4A on a GaAs substrate, since the GaAs substrate itself has a high resistance, it is necessary to obtain both of the positive pole and negative pole of the diode at the substrate surface, the structure becomes complex, and obtaining the ability as a protection device becomes difficult. Further, in order to configure the diode, use is made of a PN junction, Schottky junction, etc., but basically this junction is not strong against ESD etc., so it is difficult to obtain a high performance ESD device.
Further, this junction portion has a large parasitic capacitance; therefore, it is apt to exert an adverse influence upon the high frequency characteristic.
A high frequency integrated circuit 50 of a conventional example not having a protection device is shown in FIG. 5. In FIG. 5, a drain of a DFET1C (depletion type field effect transistor) 53 is connected to an input/output terminal I/O 52 of a high frequency circuit 51, its source is connected to one terminal of a capacitor C50 (55), and the other terminal of the capacitor C50 is connected to the GND (ground). Further, the gate is connected via a resistor 54 to a control terminal (CTL3).
Here, the resistor configuring the DC bias of the DFET1C (53) is omitted. Only the circuit relating to the high frequency (AC) signal is shown.
A reference voltage is applied from the CTL3 via the resistor 54 to the gate of the DFET1C (53) to turn it ON/OFF and make it function as a switch.
When applying a predetermined voltage to this CTL3 terminal and turning the DFET1C (53) ON, even if a high frequency signal is input from the I/O input terminal 52, current flows via the drain and source of the DFET1C and the capacitor C50, and a high frequency signal is not input to the high frequency circuit 51.
Next, the DFET1C is turned OFF and the input signal is supplied to the high frequency circuit 51. In this state, assuming that for example a high voltage noise or high voltage pulse is applied to the I/O input terminal 52, a D field effect transistor (DFET1C) 53 is usually in the OFF state. Since the output impedance of the DFEI1C is high, a pulse current cannot rapidly be sent to the capacitor C50 and is input to the input or output of the high frequency circuit 51. As a result, internal devices of the high frequency circuit 51 are broken.
An example of providing a protection device at the input terminal or output terminal of a high frequency circuit 61 for improving the circuit of FIG. 5 is shown next. FIG. 6 shows another conventional example obtained by adding a protection diode to the high frequency integrated circuit 50 shown in FIG. 5. In FIG. 6, the drain of a D field effect transistor (DFET1D: Depletion type field effect transistor) 63 is connected to an input/output terminal I/O 62 of the high frequency circuit 61, its source is connected to one terminal of a capacitor C60 (67), and the other terminal of the capacitor C60 is connected to the GND. The source is further connected to a cathode of a diode 65, and an anode is connected to the anode of a diode 66. The cathode of the diode 66 is connected to the GND. Further, the gate of the D field effect transistor 63 is connected via a resistor 64 to a control 5 (CTL5).
The reference voltage is applied from the CTL5 via the resistor 64 to the gate of the D field effect transistor 63.
Between the source of the D field effect transistor 63 and the GND, a protection device using two diodes 65 and 66, having anodes commonly connected, having cathodes arranged at both ends, having one cathode connected to the source of the D field effect transistor 1D63, and having the other cathode connected to the GND is provided. The electrical input/output characteristics of this protection device are that a current does not flow and the resistance becomes high when the input voltage is smaller than an absolute value of the voltages of Vb+Vf in both of the forward direction and the reverse direction and that the current abruptly flows and the resistance becomes low when the input voltage is larger than the absolute value of Vb+Vf.
When high voltage noise or a high voltage pulse from the input/output terminal I/O (62) is input, since the D field effect transistor 1D63 is in a floating state, the drain and the source become conductive. When the input voltage becomes equal to the added withstand voltages of the diodes 65 and 66 or more, as explained above, the diodes 65 and 66 break down, and the combined resistance value thereof changes from a high resistance to a low resistance. As a result, charges are discharged via the diodes 65 and 66 forming a low resistance current passage to the GND, and noise or a high voltage pulse is no longer applied to the high frequency circuit 61.
However, in the example of this high frequency integrated circuit equipped with a protection diode, in the same way as FIG. 4A, when the diodes 65 and 66 are formed on the GaAs substrate, since the GaAs substrate itself has a high resistance, it is necessary to obtain both of the positive poles and negative poles of the diodes at the substrate surface, the structure becomes complex, and it is difficult to draw out the capability as a protection device. Further, in order to configure the diodes, use is made of a PN junction, Schottky junction, etc., but basically this junction is not strong against ESD etc., so it is difficult to obtain a high performance ESD device.
Further, this junction portion has a large parasitic capacitance, therefore is apt to exert an adverse influence upon the high frequency characteristics.    Patent Document 1: Japanese Patent Publication (A) No. 6-13862    Patent Document 2: Japanese Patent Publication (A1) No. 2000-510653